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integrated device technology, inc. commercial temperature range december 1996 1996 integrated device technology, inc. dsc-3022/3 cmos syncbififo ? 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2 functional block diagram idt723622 IDT723632 idt723642 features: free-running clka and clkb may be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) two independent clocked fifos buffering data in oppo- site directions memory storage capacity: idt723622?56 x 36 x 2 IDT723632?12 x 36 x 2 idt723642?024 x 36 x 2 mailbox bypass register for each fifo programmable almost-full and almost-empty flags microprocessor interface control logic ira, ora, aea , and afa flags synchronized by clka ? irb, orb, aeb , and afb flags synchronized by clkb ? supports clock frequencies up to 67mhz mail 1 register programmable flag offset registers input register output register 256 x 36 512 x 36 1024 x 36 sram write pointer read pointer status flag logic input register output register 256 x 36 512 x 36 1024 x 36 sram write pointer read pointer status flag logic clka csa w/ r a ena mba port-a control logic fifo1, mail1 reset logic rst1 mail 2 register mbf2 clkb csb w /rb enb mbb port-b control logic fifo2, mail2 reset logic rst2 mbf1 fifo 1 fifo 2 9 orb aeb 36 36 irb afb b 0 - b 35 ira afa fs 0 fs 1 a 0 - a 35 ora aea 3022 drw 01 36 36 ? fast access times of 11ns ? available in 132-pin plastic quad flatpack (pqf) or space-saving 120-pin thin quad flatpack (pf) ? low-power 0.8-micron advanced cmos technology ? industrial temperature range (-40 o c to +85 o c) is avail- able, tested to military electrical specifications description: the idt723622/723632/723642 is a monolithic, high-speed, low-power, cmos bidirectional syncfifo (clocked) memory which supports clock frequencies up to 67mhz and have read access times as fast as 11ns. two independent 256/512/ 1024x36 dual-port sram fifos on board each chip buffer data in opposite directions. each fifo has flags to indicate empty and full conditions and two programable flags (almost syncfifo is a trademark and the idt logo is a registered trademark of integrated device technology, inc. 5.22 for latest information contact idt's web site at www.idt.com or fax-on-demand at 408-492-8391.
5.22 2 idt723622/723632/723642 cmos syncbififo ? 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2 commercial temperature range description (continued) full and almost empty) to indicate when a selected number of words is stored in memory. communication between each port may bypass the fifos via two 36-bit mailbox registers. each mailbox register has a flag to signal when new mail has been stored. two or more devices may be used in parallel to create wider data paths. the idt723622/723632/723642 is a synchronous (clocked) fifo, meaning each port employs a synchronous interface. all data transfers through a port are gated to the low-to- high transition of a port clock by enable signals. the clocks for each port are independent of one another and can be notes: 1. nc ?no internal connection 2. uses yamaichi socket ic51-1324-828 nc nc a 35 a 34 a 33 a 32 v cc a 31 a 30 gnd a 29 a 28 a 27 a 26 a 25 a 24 a 23 gnd a 22 v cc a 21 a 20 a 19 a 18 gnd a 17 a 16 a 15 a 14 a 13 v cc a 12 nc nc b 35 b 34 b 33 b 32 gnd b 31 b 30 b 29 b 28 b 27 b 26 v cc b 25 b 24 gnd b 23 b 22 b 21 b 20 b 19 b 18 gnd b 17 b 16 v cc b 15 b 14 b 13 b 12 gnd nc nc 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 pq132-1 3022 drw 02 nc nc nc v cc clkb enb w /rb csb gnd irb orb afb aeb v cc mbf1 mbb rst2 fs1 gnd fs0 rst1 mba mbf2 aea afa v cc ora ira csa w/ r a ena clka gnd 117 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 nc nc b 11 b 10 b 9 b 7 b 8 v cc b 6 gnd b 5 b 4 b 3 b 2 b 1 b 0 gnd a 0 a 1 a 2 v cc a 3 a 4 a 5 gnd a 6 a 7 a 8 a 9 a 10 a 11 gnd nc 74 76 77 78 79 80 81 82 83 75 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 pin configuration pqf package top view asynchronous or coincident. the enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. the input ready (ira, irb) and almost-full ( afa , afb ) flags of a fifo are two-stage synchronized to the port clock that writes data into its array. the output ready (ora, orb) and almost-empty ( aea , aeb ) flags of a fifo are two-stage synchronized to the port clock that reads data from its array. offset values for the almost-full and almost-empty flags of both fifos can be programmed from port a. the idt723622/723632/723642 is characterized for op- eration from 0 c to 70 c.
5.22 3 idt723622/723632/723642 cmos syncbififo ? 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2 commercial temperature range pin configuration tqfp top view pn120-1 3022 drw 03 a 35 a 34 a 33 a 32 v cc a 31 a 30 gnd a 29 a 28 a 27 a 26 a 25 a 24 a 23 gnd a 22 v cc a 21 a 20 a 19 a 18 gnd a 17 a 16 a 15 a 14 a 13 v cc a 12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 b 35 b 34 b 33 b 32 gnd b 31 b 30 b 29 b 28 b 27 b 26 v cc b 25 b 24 gnd b 23 b 22 b 21 b 20 b 19 b 18 gnd b 17 b 16 v cc b 15 b 14 b 13 b 12 gnd 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 91 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 v cc gnd clka ena w/ r a csa ira ora v cc afa aea mbf2 mba rst1 fs0 gnd fs1 rst2 mbb mbf1 v cc aeb afb orb irb gnd csb w /rb enb clkb gnd a 11 a 10 a 9 a 8 a 7 a 6 gnd a 5 a 4 a 3 v cc a 2 a 1 a 0 gnd b 0 b 1 b 2 b 3 b 4 b 5 gnd b 6 v cc b 7 b 8 b 9 b 10 b 11 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
5.22 4 idt723622/723632/723642 cmos syncbififo ? 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2 commercial temperature range pin descriptions symbol name i/o description a0-a35 port-a data i/0 36-bit bidirectional data port for side a. aea port-a almost o programmable almost-empty flag synchronized to clka. it is low -empty flag (port a) when the number of words in fif02 is less than or equal to the value in the almost-empty a offset register, x2. aeb port-b almost o programmable almost-empty flag synchronzed to clkb. it is low -empty flag (port b) when the number of words in fif01 is less than or equal to the value in the almost-empty b offset register, x1. afa port-a almost o programmable almost-full flag synchronized to clka. it is low when -full flag (port a) the number of empty locations in fif01 is less than or equal to the value in the almost-full a offset register, y1. afb port-b almost o programmable almost-full flag synchronized to clkb. it is low when -full flag (port b) the number of empty locations in fif02 is less than or equal to the value in the almost-full b offset register, y2. b0 - b35 port-b data i/o 36-bit bidirectional data port for side b. clka port-a clock i clka is a continuous clock that synchronizes all data transfers through port a and can be asynchronous or coincident to clkb. ira, ora, afa , and aea are all synchronized to the low-to-high transition of clka. clkb port-b clock i clkb is a continuous clock that synchronizes all data transfers through port b and can be asynchronous or coincident to clka. irb, orb, afb , and aeb are synchronized to the low-to-high transition of clkb. csa port-a chip i csa must be low to enable to low-to-high transition of clka to read or select write on port a. the ao-a35 outputs are in the high-impedance state when csa is high. csb port-b chip i csb must be low to enable a low-to-high transition of clkb to read or select write data on port b. the bo- b35 outputs are in the high-impedance state when csb is high. ena port-a enable i ena must be high to enable a low-to-high transition of clka to read or write data on port a. enb port-b enable i enb must be high to enable a low-to-high transition of clkb to read or write data on port b. fs1, flag offset i the low-to-high transition of a flfos reset input latches the values of fso fs0 selects and fs1. if either fso or fs1 is high when a reset input goes high, one of the three preset values is selected as the offset for the flfos almost-full and almost-empty flags. if both fifos are reset simultaneously and both fso and fs1 are low when rst1 and rst2 go high, the first four writes to fifo1 almost empty offsets for both flfos. ira input-ready o ira is synchronized to the low-to-high transition of clka. when ira is flag (port a) low, fifo1 is full and writes to its array are disabled. ira is set low when fifo1 is reset and is set high on the second low-to-high transition of clka after reset. irb input-ready o irb is synchronized to the low-to-high transition of clkb. when irb is flag (port b) low, fifo2 is full and writes to its array are disabled. irb is set low when fifo2 is reset and is set high on the second low-to-high transition of clkb after reset. mba port-a mailbox i a high level on mba chooses a mailbox register for a port-a read or select write operation. when the ao-a35 outputs are active, a high level on mba selects data from the mail2 register for output and a low level selects fif02 output-register data for output.
5.22 5 idt723622/723632/723642 cmos syncbififo ? 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2 commercial temperature range symbol name i/o description mbb port-b mailbox i a high level on mbb chooses a mailbox register for a port-b read or select write operation. when the b0-b35 outputs are active, a high level on mbb selects data from the mail1 register or output and a low level selects fifo1 output-register data for output. mbf1 mail1 register o mbf1 is set low by a low-to-high transition of clka that writes data flag to the mail1 register. writes to the mail1 register are inhibited while mbf1 is low. mbf1 is set high by a low-to-high transition of clkb when a port-b read is selected and mbb is high. mbf1 is set high when fifo1 is reset. mbf2 mail2 register o mbf2 is set low by a low-to-high transition of clkb that writes data to the flag mail2 register. writes to the mail2 register are inhibited while mbf2 is low. mbf2 is set high by a low-to-high transition of clka when a port-a read is selected and mba is high. mbf2 is also set high when fifo2 is reset. ora output-ready o ora is synchronized to the low-to-high transition of clka. when ora is flag (port a) low, fifo2 is empty and reads from its memory are disabled. ready data is present on the output register of fifo2 when ora is high. ora is forced low when flfo2 is reset and goes high on the third low-to-high transition of clka after a word is loaded to empty memory. orb output-ready o orb is synchronized to the low-to-high transition of clkb. when orb flag (port b) is low, flfo1 is empty and reads from its memory are disabled. ready data is present on the output register of fifo1 when orb is high. orb is forced low when fifo1 is reset and goes high on the third low-to-high transition of clkb after a word is loaded to empty memory. rst1 fifo1 reset i to reset fifo1, four low-to-high transitions of clka and four low-to-high transitions of clkb must occur while rst1 is low. the low-to-high transition of rst1 latches the status of fso and fs1 for afa and aeb offset selection. fifo1 must be reset upon power up before data is written to its ram. rst2 fifo2 reset i to reset fifo2, four low-to-high transitions of clka and four low-to-high transitions of clkb must occur while rst2 is low. the low-to-high transition of rst2 latches the status of fso and fs1 for afb and aea offset selection. fifo2 must be reset upon power up before data is written to its ram. w/ r a port-a write/ i a high selects a write operation and a low selects a read operation on port a read select for a low-to-high transition of clka. the ao-a35 outputs are in the high impedance state when w/ r a is high. w /rb port-b write/ i a low selects a write operation and a high selects a read operation on port b read select for a low-to-high transition of clkb. the bo-b35 outputs are in the high impedance state when w /rb is low. pin descriptions (cont.)
5.22 6 idt723622/723632/723642 cmos syncbififo ? 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2 commercial temperature range absolute maximum ratings over operating free-air temperature range (un- less otherwise noted) (1) symbol rating commercial unit v cc supply voltage range -0.5 to 7 v v i (2) input voltage range -0.5 to v cc +0.5 v v o (2) output voltage range -0.5 to v cc +0.5 v i ik input clamp current (v i < 0 or v i > v cc ) 20 ma i ok output clamp current (v o = < 0 or v o > v cc ) 50 ma i out continuous output current (v o = 0 to v cc ) 50 ma i cc continuous current through v cc or gnd 400 ma t a operating free air temperature range 0 to 70 c t stg storage temperature range -65 to 150 c notes: 1. stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. the input and output voltage ratings may be exceeded provided the input and output current ratings are observed. recommended operating conditions symbol parameter min. max. unit v cc supply voltage 4.5 5.5 v v ih high-level input voltage 2 v v il low-level input voltage 0.8 v i oh high-level output current -4 ma i ol low-level output current 8 ma t a operating free-air 0 70 c temperature
5.22 7 idt723622/723632/723642 cmos syncbififo ? 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2 commercial temperature range idt723622 IDT723632 idt723642 commerical t a = 15, 20, 30 ns parameter test conditions min. typ. (1) max. unit v oh v cc = 4.5v, i oh = -4 ma 2.4 v v ol v cc = 4.5 v, i ol = 8 ma 0.5 v i li v cc = 5.5 v, v i = v cc or 0 5 m a i lo v cc = 5.5 v, v o = v cc or 0 5 m a i cc v cc = 5.5 v, v i = v cc -0.2 v or 0 400 m a d i cc (2) v cc = 5.5 v, one input at 3.4 v, csa = vih a0-a35 0 ma other inputs at v cc or gnd csb = vih b0-b35 0 csa = vil a0-a35 1 csb = vil b0-35 1 all other inputs 1 c in v i = 0, f = 1 mhz 4 pf c out v o = 0, f = 1 mhz 8 pf electrical characteristics over recommended operating free-air tempera- ture range (unless otherwise noted) notes: 1. all typical values are at v cc = 5v, t a = 25 c. 2. this is the supply current when each input is at least one of the specified ttl voltage levels rather than 0v or v cc .
5.22 8 idt723622/723632/723642 cmos syncbififo ? 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2 commercial temperature range 723622-15 723622-20 723622-30 723632-15 723632-20 723632-30 723642-15 723642-20 723642-30 symbol parameter min. max. min. max. min. max. unit f s clock frequency, clka or clkb 66.7 50 33.4 mhz t clk clock cycle time, clka or clkb 15 20 30 ns t clkh pulse duration, clka or clkb high 6 8 10 ns t clkl pulse duration, clka and clkb low 6 8 10 ns t ds setup time, a0-a35 before clka - and b0-b35 4 5 6 ns before clkb - t ens setup time, csa , w/ r a, ena, and mba before 4.5 5 6 ns clka - ; csb , w /rb, enb, and mbb before clkb - t rsts setup time, rst1 or rst2 low before clka - 567ns or clkb - (1) t fss setup time, fs0 and fs1 before rst1 and rst2 7.5 8.5 9.5 ns high t dh hold time, a0-a35 after clka - and b0-b35 after 1 1 1 ns clkb - t enh hold time, csa , w/ r a, ena, and mba after clka - ;1 1 1 ns csb , w /rb, enb, and mbb after clkb - t rsth hold time, rst1 or rst2 low after clka - or 4 4 5 ns clkb - (1) t fsh hold time, fs0 and fs1 after rst1 and rst2 high 2 3 3 ns t skew1 (2) skew time, between clka - and clkb - for ora, 7.5 9 11 ns orb, ira, and irb t skew2 (2) skew time, between clka - and clkb - for aea ,121620ns aeb , afa , and afb notes: 1. requirement to count the clock edge as one of at least four needed to reset a fifo. 2. skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between clka cycle and clkb cycle. timing requirements over recommended ranges of supply voltage and oper- ating free-air temperature
5.22 9 idt723622/723632/723642 cmos syncbififo ? 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2 commercial temperature range notes: 1. writing data to the mail1 register when the b0-b35 outputs are active and mbb is high. 2. writing data to the mail2 register when the a0-a35 outputs are active and mba is high. switching characteristics over recommended ranges of supply voltage and operating free-air temperature, c l = 30 pf 723622l15 723622l20 723622l30 723632l15 723632l20 723632l30 723642l15 723642l20 723642l30 symbol parameter min. max. min. max. min. max. unit t a access time, clka - to a0-a35 and clkb - 311313315ns to b0-b35 t pir propagation delay time, clka - to ira and 2 8 2 10 2 12 ns clkb - to irb t por propagation delay time, clka - to ora and 1 8 1 10 1 12 ns clkb - to orb t pae propagation delay time, clka - to aea and 1 8 1 10 1 12 ns clkb - to aeb t paf propagation delay time, clka - to afa and 1 8 1 10 1 12 ns and clkb - to afb t pmf propagation delay time, clka - to mbf1 low or 0 8 0 10 0 12 ns mbf2 high and clkb - to mbf2 low or mbf1 high t pmr propagation delay time, clka - to b0-b35 (1) and 3 13.5 3 15 3 17 ns clkb - to a0-a35 (2) t mdv propagation delay time, mba to a0-a35 valid and 3 11 3 13 3 15 ns mbb to b0-b35 valid t prf propagation delay time, rst1 low to aeb low, 1 15 1 20 1 30 ns afa high, and mbf1 high, and rst2 low to aea low, afb high, and mbf2 high t en enable time, csa and w/ r a low to a0-a35 active 2 12 2 13 2 14 ns and csb low and w /rb high to b0-b35 active t dis disable time, csa or w/ r a high to a0-a35 at 1 8 1 10 1 11 ns high impedance and csb high or w /rb low to b0-b35 at high impedance
5.22 10 idt723622/723632/723642 cmos syncbififo ? 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2 commercial temperature range fs1 fs0 rst1 rst1 rst2 rst2 x1 and y1 reglsters (1) x2 and y2 reglsters (2) hh - x64 x hh x - x64 hl - x16 x hl x - x16 lh - x8 x lh x - x8 ll -- programmed from port a programmed from port a notes: 1. x1 register holds the offset for aeb ; y1 register holds the offset for afa . 2. x2 register holds the offset tor aea ; y2 register holds the offset for afb . table 1. flag programming during the low-to-high transition of its reset input. for example, to load the preset value of 64 into x1 and y1, fs0 and fs1 must be high when flfo1 reset ( rst1 ) returns high. flag-offset registers associated with fifo2 are loaded with one of the preset values in the same way with fifo2 reset ( rst2 ). when using one of the preset values for the flag offsets, the flfos can be reset simultaneously or at different times. to program the x1, x2, y1, and y2 registers from port a, both flfos should be reset simultaneously with fs0 and fs1 low during the low-to-high transition of the reset inputs. after this reset is complete, the first four writes to fifo1 do not store data in ram but load the offset registers in the order y1, x1, y2, x2. the port a data inputs used by the offset registers are (a7-a0), (a8-a0), or (a9-a0) for the idt723622, IDT723632, or idt723642, respectively. the highest num- bered input is used as the most significant bit of the binary number in each case. valid programming values for the registers ranges from 1 to 252 for the idt723622; 1 to 508 for the IDT723632; and 1 to 1020 for the idt723642. after all the offset registers are programmed from port a, the port-b input- ready flag (irb) is set high, and both fifos begin normal operation. fifo write/read operation the state of the port-a data (a0-a35) outputs is controlled by port-a chip select ( csa ) and port-a write/read select (w/ r a). the a0-a35 outputs are in the high-impedance state when either csa or w/ r a is high. the a0-a35 outputs are active when both csa and w/ r a are low. data is loaded into fifo1 from the a0-a35 inputs on a low-to-high transition of clka when csa is low, w/ r a is high, ena is high , mba is low, and ira is high. data is read from fifo2 to the a0-a35 outputs by a low-to-high transition of clka when csa is low, w/ r a is low, ena is high, mba is low, and ora is high (see table 2). fifo reads and writes on port a are independent of any concurrent signal description reset the fifo memories of the idt723622/723632/723642 are reset separately by taking their reset ( rst1 , rst2 ) inputs low for at least four port-a clock (clka) and four port-b clock (clkb) low-to-high transitions. the reset inputs can switch asynchronously to the clocks. a fifo reset initializes the internal read and write pointers and forces the input-ready flag (ira, irb) low, the output-ready flag (ora, orb) low, the almost-empty flag ( aea , aeb ) low, and the almost-full flag ( afa , afb ) high. resetting a fifo also forces the mailbox flag ( mbf1 , mbf2 ) of the parallel mailbox register high. after a flfo is reset, its input-ready flag is set high after two clock cycles to begin normal operation. a fifo must be reset after power up before data is written to its memory. a low-to high transition on a flfo reset ( rst1 , rst2 ) input latches the value of the flag-select (fs0, fs1) inputs for choosing the almost-full and almost-empty offset program- ming method (see almost-empty and almost-full flag offset programming below). almost-empty flag and almost-full flag off- set programming four registers in the idt723622/723632/723642 are used to hold the offset values for the almost-empty and almost-full flags. the port-b almost-empty flag ( aeb ) offset register is labeled x1 and the port-a almost-empty flag ( aea ) offset register is labeled x2. the port-a almost-full flag ( afa ) offset register is labeled y1 and the port-b almost-full flag ( afb ) offset register is labeled y2. the index of each register name corresponds to its fifo number. the offset registers can be loaded with preset values during the reset of a fifo or they can be programmed from port a (see table 1 ) . to load a fifo almost-empty flag and almost-full flag offset registers with one of the three preset values listed in table1, at least one of the flag-select inputs must be high
5.22 11 idt723622/723632/723642 cmos syncbififo ? 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2 commercial temperature range csa csa w/ r r a ena mba clka a0-a35 outputs port function h x x x x in high-impedance state none l h l x x in high-impedance state none lhhl - in high-impedance state fifo1 write lhhh - in high-impedance state mail1 write l l l l x active, fifo2 output register none llhl - active, fifo2 output register fifo2 read l l l h x active, mail2 register none llhh - active, mail2 register mail2 read (set mbf2 high) csb csb w w /rb enb mbb clkb b0-b35 outputs port function h x x x x in high-impedance state none l l l x x in high-impedance state none llhl - in high-impedance state fifo2 write llhh - in high-impedance state mail2 write l h l l x active, fifo1 output register none lhhl - active, fifo1 output register fifo1 read l h l h x active, mail1 register none lhhh - active, mail1 register mail1 read (set mbf1 high) table 3. port-b enable function table table 2. port-a enable functlon table port-b operation. the port-b control signals are identical to those of port a with the exception that the port-b write/read select ( w /rb) is the inverse of the port-a write/read select (w/ r a). the state of the port-b data (b0-b35) outputs is controlled by the port- b chip select ( csb ) and port-b write/read select ( w /rb). the b0-b35 outputs are in the high-impedance state when either csb is high or w /rb is low. the b0-b35 outputs are active when csb is low and w /rb is high. data is loaded into fifo2 from the b0-b35 inputs on a low-to-high transition of clkb when csb is low, w /rb is low, enb is high, mbb is low, and irb is high. data is read from fifo1 to the b0-b35 outputs by a low-to-high transition of clkb when csb is low, w /rb is high, enb is high, mbb is low, and orb is high (see table 3) . fifo reads and writes on port b are independent of any concurrent port-a operation. the setup and hold time constraints to the port clocks for the port chip selects and write/read selects are only for enabling write and read operations and are not related to high- impedance control of the data outputs. if a port enable is low during a clock cycle, the ports chip select and write/read select may change states during the setup and hold time window of the cycle. when a fifo output-ready flag is low, the next data word is sent to the fifo output register automatically by the low-to-high transition of the port clock that sets the output- ready flag high. when the output-ready flag is high, an available data word is clocked to the fifo output register only when a fifo read is selected by the ports chip select, write/ read select, enable, and mailbox select. synchronized fifo flags each fifo is synchronized to its port clock through at least two flip-flop stages. this is done to improve flag-signal reliability by reducing the probability of metastable events when clka and clkb operate asynchronously to one an- other. ora, aea , ira, and afa are synchronized to clka. orb, aeb , irb, and afb are synchronized to clkb. tables 4 and 5 show the relationship of each port flag to fifo1 and fif02.
5.22 12 idt723622/723632/723642 cmos syncbififo ? 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2 commercial temperature range occurs, simultaneously forcing the output-ready flag high and shifting the word to the fifo output register. a low-to-high transition on an output-ready flag syn- chronizing clock begins the first synchronization cycle of a write if the clock transition occurs at time t skew1 or greater after the write. otherwise, the subsequent clock cycle can be the first synchronization cycle (see figures 7 and 8). input-ready flags (ira, irb) the input-ready flag of a flfo is synchronized to the port clock that writes data to its array. when the input-ready flag is high, a memory location is free in the sram to receive new data. no memory locations are free when the input-ready flag is low and attempted writes to the fifo are ignored. each time a word is written to a fifo, its write pointer is incremented. the state machine that controls an input-ready flag monitors a write pointer and read pointer comparator that indicates when the flfo sram status is full, full-1, or full-2. from the time a word is read from a fifo, its previous memory location is ready to be written in a minimum of two cycles of the s s ynchronized synchronized number of words in fifo to clkb to clka idt723622 (1,2) IDT723632 (1,2) idt723642 (1,2) orb aeb aeb afa afa ira 000llhh 1 to x1 1 to x1 1 to x1 h l h h (x1+1) to [256-(y1+1)] (x1+1) to [512-(y1+1)] (x1+1) to [1024-(y1+1)] h h h h (256-y1) to 255 (512-y1) to 511 (1024-y1) to 1023 h h l h 256 512 1024 h h l l table 4. fif01 flag operatlon notes: 1. x1 is the almost-empty offset for fifo1 used by aeb . y1 is the almost-full offset for fifo1 used by afa . both x1 and y1 are selected during a reset of fifo1 or programmed from port a. 2. when a word loaded to an empty fifo is shifted to the output register, its previous fifo memory location is free. s s ynchronized synchronized number of words in fifo to clka to clkb idt723622 (1,2) IDT723632 (1,2) idt723642 (1,2) ora aea aea afb afb irb 000llhh 1 to x2 1 to x2 1 to x2 h l h h (x2+1) to [256-(y2+1)] (x2+1) to [512-(y2+1)] (x2+1) to [1024-(y2+1)] h h h h (256-y2) to 255 (512-y2) to 511 (1024-y2) to 1023 h h l h 256 512 1024 h h l l table 5. fif02 flag operatlon notes: 1. x2 is the almost-empty offset for fifo2 used by aea . y2 is the almost-full offset for fifo2 used by afb . both x2 and y2 are selected during a reset of fifo2 or programmed from port a. 2. when a word loaded to an empty fifo is shifted to the output register, its previous fifo memory location is free. output-ready flags (ora, orb) the output-ready flag of a fifo is synchronized to the port clock that reads data from its array. when the output-ready flag is high, new data is present in the fifo output register. when the output-ready flag is low, the previous data word is present in the fifo output register and attempted fifo reads are ignored. a fifo read pointer is incremented each time a new word is clocked to its output register. the state machine that controls an output-ready flag monitors a write pointer and read pointer comparator that indicates when the fifo sram status is empty, empty+1, or empty+2. from the time a word is written to a fifo, it can be shifted to the fifo output register in a minimum of three cycles of the output-ready flag synchro- nizing clock. therefore, an output-ready flag is low if a word in memory is the next data to be sent to the flfo output register and three cycles of the port clock that reads data from the fifo have not elapsed since the time the word was written. the output-ready flag of the fifo remains low until the third low-to-high transition of the synchronizing clock
5.22 13 idt723622/723632/723642 cmos syncbififo ? 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2 commercial temperature range almost-empty flag and almost-full flag offset programming above). an almost-full flag is low when the number of words in its fifo is greater than or equal to (256-y), (512-y), or (1024-y) for the idt723622, IDT723632, or idt723642 re- spectively. an almost-full flag is high when the number of words in its fifo is less than or equal to [256-(y+1)], [512- (y+1)], or [1024-(y+1)] for the idt723622, IDT723632, or idt723642 respectively. note that a data word present in the fifo output register has been read from memory. two low-to-high transitions of the almost-full flag syn- chronizing clock are required after a fifo read for its almost- full flag to reflect the new level of fill. therefore, the almost-full flag of a fifo containing [256/512/1024-(y+1)] or less words remains low if two cycles of its synchronizing clock have not elapsed since the read that reduced the number of words in memory to [256/512/1024-(y+1)]. an almost-full flag is set high by the second low-to-high transition of its synchro- nizing clock after the fifo read that reduces the number of words in memory to [256/512/1024-(y+1)]. a low-to-high transition of an almost-full flag synchronizing clock begins the first synchronization cycle if it occurs at time t skew2 or greater after the read that reduces the number of words in memory to [256/512/1024-(y+1)]. otherwise, the subsequent synchro- nizing clock cycle may be the first synchronization cycle (see figures 13 and 14). mailbox registers each fifo has a 36-bit bypass register to pass command and control information between port a and port b without putting it in queue. the mailbox-select (mba, mbb) inputs choose between a mail register and a fifo for a port data transfer operation. a low-to-high transition on clka writes a0-a35 data to the mail1 register when a port-a write is selected by csa , w/ r a, and ena and with mba high. a low-to-high transition on clkb writes bo-b35 data to the mail2 register when a port-b write is selected by csb , w /rb, and enb and with mbb high. writing data to a mail register sets its corresponding flag ( mbf1 or mbf2 ) low. attempted writes to a mail register are ignored while the mail flag is low. when data outputs of a port are active, the data on the bus comes from the fifo output register when the port mailbox select input is low and from the mail register when the port- mailbox select input is high. the mail1 register flag ( mbf1 ) is set high by a low-to-high transition on clkb when a port-b read is selected by csb , w /rb, and enb and with mbb high. the mail2 register flag ( mbf2 ) is set high by a low- to-high transition on clka when a port-a read is selected by csa , w/ r a, and ena and with mba high. the data in a mail register remains intact after it is read and changes only when new data is written to the register. input-ready flag synchronizing clock. therefore, an input- ready flag is low if less than two cycles of the input-ready flag synchronizing clock have elapsed since the next memory write location has been read. the second low-to-high transition on the input-ready flag synchronizing clock after the read sets the input-ready flag high. a low-to-high transition on an input-ready flag syn- chronizing clock begins the first synchronization cycle of a read if the clock transition occurs at time t skew1 or greater after the read. otherwise, the subsequent clock cycle can be the first synchronization cycle (see figures 9 and 10). almost-empty flags ( aea , aeb ) the almost-empty flag of a fifo is synchronized to the port clock that reads data from its array. the state machine that controls an almost-empty flag monitors a write pointer and read pointer comparator that indicates when the fifo sram status is almost empty, almost empty+1, or almost empty+2. the almost-empty state is defined by the contents of register x1 for aeb and register x2 for aea . these registers are loaded with preset values during a fifo reset or programmed from port a (see almost-empty flag and almost-full flag offset programming above). an almost empty flag is low when its fifo contains x or less words and is high when its fifo contains (x+1) or more words. a data word present in the fifo output register has been read from memory. two low-to-high transitions of the almost-empty flag synchronizing clock are required after a fifo write for its almost-empty flag to reflect the new level of fill. therefore, the almost-full flag of a fifo containing (x+1) or more words remains low if two cycles of its synchronizing clock have not elapsed since the write that filled the memory to the (x+1) level. an almost-empty flag is set high by the second low- to-high transition of its synchronizing clock after the fifo write that fills memory to the (x+1) level. a low-to-high transition of an almost-empty flag synchronizing clock begins the first synchronization cycle if it occurs at time t skew2 or greater after the write that fills the fifo to (x+1) words. otherwise, the subsequent synchronizing clock cycle may be the first synchronization cycle. (see figures 11 and 12). almost-full flags ( afa afa , afb afb ) the almost-full flag of a fifo is synchronized to the port clock that writes data to its array. the state machine that controls an almost-full flag monitors a write pointer and read pointer comparator that indicates when the fifo sram status is almost full, almost full-1, or almost full-2. the almost- full state is defined by the contents of register y1 for afa and register y2 for afb . these registers are loaded with preset values during a flfo reset or programmed from port a (see
5.22 14 idt723622/723632/723642 cmos syncbififo ? 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2 commercial temperature range clka rst1 ira aeb afa mbf1 clkb orb fs1,fs0 3022 drw 04 t rsts t rsth t fsh t fss t pir t pir t por t rsf 0,1 t rsf t rsf figure 1. fifo1 reset loading x1 and y1 with a preset value of eight (1) . note: 1. fifo2 is reset in the same manner to load x2 and y2 with a preset value. 3022 drw 05 clka rst1 , rst2 ira clkb irb a0 - a35 fs1,fs0 ena t fss t fsh t pir t enh t ens t skew1 t ds t dh t pir 4 0,0 afa offset (y1) aeb offset (x1) afb offset (y2) aea offset (x2) first word to fifo1 1 2 (1) notes: 1. t skew1 is the minimum time between the rising clka edge and a rising clkb edge for irb to transition high in the next cycle. if the time between the rising edge of clka and rising edge of clkb is less than t skew1 , then irb may transition high one cycle later than shown. 2. csa = low, w/ r a = high, mba = low. it is not necessary to program offset register on consecutive clock cycles. figure 2. programming the almost-full flag and almost-empty flag offset values after reset.
5.22 15 idt723622/723632/723642 cmos syncbififo ? 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2 commercial temperature range 3022 drw 06 clka ira ena a0 - a35 mba csa w/ r a t clkh t clkl t clk t ens t ens t ens t ens t ds t enh t enh t enh t enh t dh w1 (1) w2 (1) t ens t enh t enh t ens no operation note: 1. written to fifo1. figure 3. port-a write cycle timing for fifo1 3022 drw 07 clkb irb enb b0 - b35 mbb csb w /rb t clk t clkh t clkl t enh t enh t enh t enh t dh w1 (1) w2 (1) t ens t ds t ens t ens t ens t ens t enh t enh t ens no operation note: 1. written to fifo2. figure 4. port-b write cycle timing for fifo2.
5.22 16 idt723622/723632/723642 cmos syncbififo ? 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2 commercial temperature range 3022 drw 08 clkb orb enb b0 - b35 mbb csb w /rb t clk t clkh t clkl t ens t a t mdv t en t a t ens t enh t ens t enh w1 w2 w3 (1) (1) (1) t enh t dis no operation note: 1. read from fifo1. figure 5. port-b read cycle timing for fifo1. note: 1. read from fifo2. figure 6. port-a read cycle timing for fifo2. 3022 drw 09 clka ora ena a0 - a35 mba csa w/ r a t clk t clkh t clkl t ens t dmv t en t a t a t enh t ens t enh t ens t enh w1 w2 w3 (1) (1) (1) t dis no operation
5.22 17 idt723622/723632/723642 cmos syncbififo ? 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2 commercial temperature range csa w r a mba ira a0 - a35 clkb orb csb w /rb mbb ena enb b0 -b35 clka 3022 drw 10 12 3 t clkh t clkl t clk t ens t ens t enh t enh t ds t dh t skew1 t clk t clkl t por t por t ens t enh t a old data in fifo1 output register w1 old data in fifo1 output register low high low high low t clkh w1 high (1) note: 1. t skew1 is the minimum time between a rising clka edge and a rising clkb edge for orb to transition high and to clock the next word to the fifo1 output register in three clkb cycles. if the time between the rising clka edge and rising clkb edge is less than t skew1 , then the transition of orb high and load of the first word to the output register may occur one clkb cycle later than shown. figure 7. orb flag timing and first data word fallthrough when fifo1 is empty.
5.22 18 idt723622/723632/723642 cmos syncbififo ? 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2 commercial temperature range csb w /rb mbb irb b0 - b35 clka ora csa w/ r a mba enb ena a0 -a35 clkb 3022 drw 11 12 3 t clkh t clkl t clk t ens t ens t enh t enh t ds t dh t skew1 t clk t clkh t por t por t ens t enh t a old data in fifo2 output register w1 old data in fifo2 output register t clkl low low low low low high w1 (1) note: 1. t skew1 is the minimum time between a rising clkb edge and a rising clka edge for ora to transition high and to clock the next word to the fifo2 output register in three clka cycles. if the time between the rising clkb edge and rising clka edge is less than t skew1 , then the transition of ora high and load of the first word to the output register may occur one clka cycle later than shown. figure 8. ora flag timing and first data word fallthrough when fifo2 is empty.
5.22 19 idt723622/723632/723642 cmos syncbififo ? 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2 commercial temperature range csb orb w /rb mbb enb b0 -b35 clkb ira clka csa 3022 drw 12 w r a a0 - a35 mba ena 12 t clk t clkh t clkl t ens t enh t a t skew1 t clk t clkh t clkl t pir t pir t ens t ens t ds t enh t enh t dh to fifo1 previous word in fifo1 output register next word from fifo1 low high low high low high (1) fifo1 full note: 1. t skew1 is the minimum time between a rising clkb edge and a rising clka edge for ira to transition high in the next clka cycle. if the time between the rising clkb edge and rising clka edge is less than t skew1 , then ira may transition high one clka cycle later than shown. figure 9. ira flag timing and first available write when fifo1 is full.
5.22 20 idt723622/723632/723642 cmos syncbififo ? 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2 commercial temperature range csa ora w/ r a mba ena a0 -a35 clka irb clkb csb 3022 drw 13 w rb b0 - b35 mbb enb 12 t clk t clkh t clkl t ens t enh t a t skew1 t clk t clkh t clkl t pir t pir t ens t ens t enh t enh t ds t dh to fifo2 previous word in fifo2 output register next word from fifo2 fifo2 full low low low high low low (1) note: 1. t skew1 is the minimum time between a rising clka edge and a rising clkb edge for irb to transition high in the next clkb cycle. if the time between the rising clka edge and rising clkb edge is less than t skew1 , then irb may transition high one clkb cycle later than shown. figure 10. irb flag timing and first available write when fifo2 is full. figure 11. timing for aeb aeb when fifo2 is almost empty. notes: 1. t skew2 is the minimum time between a rising clka edge and a rising clkb edge for aeb to transition high in the next clkb cycle. if the time between the rising clka edge and rising clkb edge is less than t skew2 , then aeb may transition high one clkb cycle later than shown. 2. fifo1 write ( csa = low, w/ r a = low, mba = low), fifo1 read ( csb = low, w /rb = high, mbb = low). data in the fifo1 output register has been read from the fifo. aeb clka enb 3022 drw 14 ena clkb 2 1 t ens t enh t skew2 t pae t pae t ens t enh x1 word in fifo1 (x1+1) words in fifo1 (1)
5.22 21 idt723622/723632/723642 cmos syncbififo ? 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2 commercial temperature range aea clkb ena 3022 drw 15 enb clka 2 1 t ens t enh t skew2 t pae t pae t ens t enh (x2+1) words in fifo2 x2 words in fifo2 (1) figure 13. timing for afa afa when fifo1 is almost full. notes: 1. t skew2 is the minimum time between a rising clka edge and a rising clkb edge for afa to transition high in the next clka cycle. if the time between the rising clka edge and rising clkb edge is less than t skew2 , then afa may transition high one clkb cycle later than shown. 2. fifo1 write ( csa = low, w/ r a = high, mba = low), fifo1 read ( csb = low, w /rb = high, mbb = low). data in the fifo1 output register has been read from the fifo. 3. d = maximum fifo depth = 256 for the 723622, 512 for the 723632, 1024 for the 723642. afa clka enb 3022 drw 16 ena clkb 12 t skew2 t ens t enh t paf t ens t enh t paf [d-(y1+1)] words in fifo1 (d-y1) words in fifo1 (1) figure 12. timing for aea aea when fifo2 is almost empty. notes: 1. t skew2 is the minimum time between a rising clkb edge and a rising clka edge for aea to transition high in the next clka cycle. if the time between the rising clkb edge and rising clka edge is less than t skew2 , then aea may transition high one clka cycle later than shown. 2. fifo2 write ( csb = low, w /rb = low, mbb = low), fifo2 read ( csa = low, w/ r a = low, mba = low). data in the fifo2 output register has been read from the fifo.
5.22 22 idt723622/723632/723642 cmos syncbififo ? 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2 commercial temperature range afb clkb ena 3022 drw 17 enb clka 12 t skew2 t ens t enh t paf t ens t enh t paf [d-(y2+1)] words in fifo2 (d-y2) words in fifo2 (1) notes: 1. t skew2 is the minimum time between a rising clkb edge and a rising clka edge for afb to transition high in the next clkb cycle. if the time between the rising clkb edge and rising clka edge is less than t skew2 , then afb may transition high one clka cycle later than shown. 2. fifo2 write ( csb = low, w /rb = low, mbb = low), fifo2 read ( csa = low, w/ r a = low, mba = low). data in the fifo2 output register has been read from the fifo. 3. d = maximum fifo depth = 256 for the 723622, 512 for the 723632, 1024 for the 723642. figure 14. timing for afb afb when fifo2 is almost full. 3022 drw 18 clka ena a0 - a35 mba csa w/ r a clkb mbf1 csb mbb enb b0 - b35 w /rb w1 t ens t enh t ds t dh t pmf t pmf t en t mdv t pmr t ens t enh t dis w1 (remains valid in mail1 register after read) fifo1 output register figure 15. timing for mail1 register and mbf1 mbf1 flag.
5.22 23 idt723622/723632/723642 cmos syncbififo ? 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2 commercial temperature range figure 16. timing for mail2 register and mbf2 mbf2 flag. 3022 drw 19 clkb enb b0 - b35 mbb csb w /rb clka mbf2 csa mba ena a0 - a35 w/ r a w1 t ens t enh t ds t dh t pmf t pmf t ens t enh t dis t en t mdv t pmr fifo2 output register w1 (remains valid in mail 2 register after read)
5.22 24 idt723622/723632/723642 cmos syncbififo ? 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2 commercial temperature range calculating power dissipation the i cc(f) current for the graph in figure 17 was taken while simultaneously reading and writing a fifo on the idt723622/723632/723642 with clka and clkb set to f s . all data inputs and data outputs change state during each clock cycle to consume the highest supply current. data outputs were disconnected to normalize the graph to a zero capacitance load. once the capacitance load per data-output channel and the number of idt723622/723632/723642 inputs driven by ttl high levels are known, the power dissipation can be calculated with the equation below. with i cc(f) taken from figure 17, the maximum power dissipation (pt) of the idt723622/723632/723642 may be calculated by: pt = vcc x [icc(f) + (n x d icc x dc)] + ? (cl x vcc 2 x fo) where: n = number of inputs driven by ttl levels d icc= increase in power supply current for each input at a ttl high level dc = duty cycle of inputs at a ttl high level of 3.4 v cl = output capacitance load fo = switching frequency of an output when no read or writes are occurring on the IDT723632, the power dissipated by a single clock (clka or clkb) input running at frequency f s is calculated by: p t = v cc x f s x 0.184 ma/mhz typical characteristics supply current vs clock frequency 010 20 30 40 50 60 70 0 50 100 250 300 v cc = 5.0 v f s ?clock frequency ?mhz f = 1/2 f data t = 25 c a c = 0pf l v cc = 4.5 v v cc = 5.5 v 3022 drw 18 200 150 i - supply current - ma cc(f) s s figure 17.
5.22 25 idt723622/723632/723642 cmos syncbififo ? 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2 commercial temperature range note: 1. includes probe and jig capacitance. figure 18. load circuit and voltage waveforms. 3022 drw 20 parameter measurement information from output under test 30 pf 1.1 k w 5 v 680 w propagation delay load circuit 3 v gnd timing input data, enable input gnd 3 v 1.5 v 1.5 v voltage waveforms setup and hold times voltage waveforms pulse durations voltage waveforms enable and disable times voltage waveforms propagation delay times 3 v gnd gnd 3 v 1.5 v 1.5 v 1.5 v 1.5 v t w output enable low-level output high-level output 3 v ol gnd 3 v 1.5 v 1.5 v 1.5 v 1.5 v ? oh ov ? gnd oh ol 1.5 v 1.5 v 1.5 v 1.5 v input in-phase output high-level input low-level input v v v v 1.5 v 3 v t s t h t plz t phz t pzl t pzh t pd t pd (1)
5.22 26 idt723622/723632/723642 cmos syncbififo ? 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2 commercial temperature range ordering information blank pf pqf 15 20 30 l 723622 723632 723642 3022 drw 22 commercial (0 c to +70 c) thin quad flat pack plastic quad flat pack commercial only clock cycle time (t clk ) speed in nanoseconds low power 256 x 36 synchronous bififo 512 x 36 synchronous bififo 1024 x 36 synchronous bififo xxxxxx idt device type xxx x x power speed package process/ temperature range

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